1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device through a damascene technique using a low dielectric constant insulating film.
2. Background Art
In recent years, the speed of semiconductor devices has increased considerably, which has raised the problem of occurrence of a transmission delay due to a reduction in the signal propagation speed attributed to the wiring resistance and the parasitic capacitances between the wires and between the wiring layers in multilayered wiring portions. This problem has tended to worsen since the wiring resistance and the parasitic capacitance increase as the wiring width and the wiring pitch decrease with increasing integration density of the devices.
In order to prevent occurrence of a signal delay due to such increases in the wiring resistance and the parasitic capacitance, attempts have been made to employ copper wiring instead of aluminum wiring, as well as using a low dielectric constant insulating film (herein referred to as a Low-k film) as an interlayer insulating film.
As is known, a damascene technique may be used to form copper wiring using a Low-k film. This technique forms copper wiring without etching it, since the etching rate of copper is more difficult to control than that of aluminum.
Description will be made of a conventional copper wiring forming process using a damascene technique with reference to FIGS. 6 and 7. It should be noted that in these figures, like numerals are used to denote like components.
First of all, a stopper film 22 is formed on a silicon substrate 21 having a copper wiring layer 20 formed therein, as shown in FIG. 6A. The copper wiring layer 20 includes a barrier metal layer 20a and a copper layer 20b. Then, after forming a Low-k film 23 on the stopper film 22, a capping film 24 is formed on the Low-k film 23, producing the structure shown in FIG. 6B. Then, the capping film 24, the Low-k film 23, and the stopper film 22 are etched, forming a via hole 25 and a wiring groove 26, as shown in FIG. 6C. After that, a barrier metal 27 is formed on the inner surfaces of the via hole 25 and the wiring groove 26, and a copper layer 28 is buried in the via hole 25 and the wiring groove 26, forming a via plug 29 and a copper wiring layer 30. Thus, the above process can form copper wiring in which the copper wiring layer 20 formed in the silicon substrate 21 is electrically connected through the via plug 29 to the copper wiring layer 30 formed above the silicon substrate 21, as shown in FIG. 6D.
Specifically in the above process, the via hole 25 is formed as follows. First of all, a resist film 31 having a predetermined pattern is formed on the capping film 24, as shown in FIG. 7A. Then, the capping film 24 and the Low-k film 23 are etched by a photolithographic technique, forming an opening 32 reaching the stopper film 22, as shown in FIG. 7B. After that, the resist film 31, which is no longer necessary, is removed through ashing, and a stopper film 22a exposed at the opening 32 is etched to form a via hole 33, as shown in FIG. 7C.
In the conventional process of etching the stopper film 22a, however, etching of the stopper film 22a inevitably leads to etching of the capping film 24. Furthermore, the Low-k film 23 is exposed at the portion of the capping film 24 which has been removed due to the etching process and therefore the portion of the Low-k film 23 under the removed capping film portion is also etched. As a result, a cross-sectional shape of the via hole 33 is partially tapered as shown in FIG. 7C. If the Low-k film 23 has a tapered cross section as shown in FIG. 7C, it is not possible to form a copper wiring structure having an opening of desired dimensions, resulting in degraded electrical characteristics of the semiconductor device.
Further, the ashing of the resist film 31 is carried out through oxygen plasma treatment, causing the problem of the Low-k film 23 being plasma-damaged and thereby changed in quality. Such damage is significant if a porous Low-k film having a dielectric constant of less than 2.5 is used.